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FQD45N03L
March 2004
FQD45N03L
N-Channel Logic Level PWM Optimized Power MOSFET
General Description
This device employs a new advanced MOSFET technology and features low gate charge while maintaining low onresistance. Optimized for switching applications, this device improves the overall efficiency of DC/DC converters and allows operation to higher switching frequencies.
Features
* Fast switching * rDS(ON) = 0.018 (Typ), VGS = 10V * rDS(ON) = 0.028 (Typ), VGS = 5V * Qg (Typ) = 9nC, VGS = 5V * Qgd (Typ) =3nC * CISS (Typ) =970pF
Applications
* DC/DC converters
D
DRAIN (FLANGE)
GATE SOURCE
G
TO-252 MOSFET Maximum Ratings TC=25C unless otherwise noted
Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) ID Continuous (TC = 100oC, VGS = 4.5V) Continuous (TC = 25oC, VGS = 10V, RJA=52oC) Pulsed PD TJ, TSTG Power dissipation Derate above 25oC Operating and Storage Temperature 20 20 8 Figure 4 41 0.33 -55 to 150 Ratings 30 20
S
Units V V A A A A W W/oC
o
C
Thermal Characteristics
RJC RJA RJA Thermal Resistance Junction to Case TO-252 Thermal Resistance Junction to Ambient TO-252 Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 3 100 52
o
C/W C/W
oC/W o
Package Marking and Ordering Information
Device Marking FQD45N03L Device FQD45N03L Package TO-252AA Reel Size 330mm Tape Width 16mm Quantity 2500 units
(c)2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
Electrical Characteristics TC = 25C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 25V VGS = 0V VGS = 20V TC= 150oC 30 1 250 100 V A nA
On Characteristics
VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A ID = 20A, VGS = 10V ID = 18A, VGS = 4.5V 1 0.018 0.028 3 0.023 0.033 V
Dynamic Characteristics
CISS COSS CRSS Qg(TOT) Qg(5) Qg(TH) Qgs Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge (VGS = 4.5V) VDD = 15V, ID = 8A VGS = 5V, RGS = 16 (VGS = 10V) VDD = 15V, ID = 8A VGS = 10V, RGS = 16 7 29 45 27 54 108 ns ns ns ns ns ns 11 47 24 28 87 78 ns ns ns ns ns ns VDS = 15V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 5V VDD = 15V VGS = 0V to 1V ID = 18A Ig = 1.0mA 970 205 80 18 9 1.0 3.5 3.0 30 16 1.5 pF pF pF nC nC nC nC nC
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Switching Characteristics
tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time
Unclamped Inductive Switching
tav Avalanche Time ID = 2.7A, L = 3mH 180 s
Drain-Source Diode Characteristics
VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 18A ISD = 9A ISD= 18A, dISD/dt = 100A/s ISD= 18A, dISD/dt = 100A/s 1.25 1.0 58 70 V V ns nC
(c)2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
Typical Characteristic
1.2 POWER DISSIPATION MULTIPLIER
TC = 25C unless otherwise noted
25
1.0 ID, DRAIN CURRENT (A)
20 VGS = 10V 15 VGS = 5V 10
0.8
0.6
0.4
5 0.2 0 0 25 50 75 100 125 150 25 50 TA , AMBIENT TEMPERATURE (oC) 75 100 125 TC, CASE TEMPERATURE (oC) 150
0
Figure 1. Normalized Power Dissipation vs Ambient Temperature
2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01
Figure 2. Maximum Continuous Drain Current vs Case Temperature
ZJC, NORMALIZED THERMAL IMPEDANCE
PDM 0.1 t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 0.01 10-5 10-4 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
Figure 3. Normalized Maximum Transient Thermal Impedance
500 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION IDM, PEAK CURRENT (A) VGS = 10V 100 VGS = 5V TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TC 125
10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
Figure 4. Peak Current Capability
(c)2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
Typical Characteristic (Continued) TC = 25C unless otherwise noted
50 PULSE DURATION = 80s 40 ID , DRAIN CURRENT (A) DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) 40 50 VGS = 10V VGS = 5V
30 TJ = 150oC 20 TJ = 25oC TJ = 0 1 2 3 4 VGS , GATE TO SOURCE VOLTAGE (V) 5 -55oC
30
VGS = 4V
20
10
10
VGS = 3V TC = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
0 0 0.5 1.0 1.5 VDS , DRAIN TO SOURCE VOLTAGE (V) 2.0
Figure 5. Transfer Characteristics
40 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) ID = 10A 30 ID = 20A
Figure 6. Saturation Characteristics
2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.5
20
1.0
VGS = 10V, ID =20A 10 2 4 6 8 10 0.5 -80 -40 VGS, GATE TO SOURCE VOLTAGE (V) 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160
Figure 7. Drain To Source On Resistance vs Gate Voltage And Drain Current
1.2 VGS = VDS, ID = 250A
Figure 8. Normalized Drain To Source On Resistance vs Junction Temperatrue
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE
ID = 250A
NORMALIZED GATE THRESHOLD VOLTAGE
1.0
1.1
0.8
1.0
0.6
0.4 -80 -40 0 40 80 120 160
0.9 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Gate Threshold Voltage vs Junction Temperature
Figure 10. Normalized Drain To Source Breakdown Voltage vs Junction Temperature
(c)2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
Typical Characteristic (Continued) TC = 25C unless otherwise noted
2000 CISS = CGS + CGD VGS , GATE TO SOURCE VOLTAGE (V) 10 VDD = 15V 8
1000 C, CAPACITANCE (pF) COSS CDS + CGD
6
CRSS = CGD
4 WAVEFORMS IN DESCENDING ORDER: ID = 20A ID = 10A 0 5 10 Qg, GATE CHARGE (nC) 15 20
100 VGS = 0V, f = 1MHz 40 0.1 1 10 30
2
0 VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Capacitance vs Drain To Source Voltage
100 VGS = 4.5V, VDD = 15V, ID = 8A 80 tr
Figure 12. Gate Charge Waveforms For Constant Gate Current
150 VGS = 10V, VDD = 15V, ID = 8A td(OFF) SWITCHING TIME (ns) 100
SWITCHING TIME (ns)
60
tf
40 td(OFF) td(ON) 20
tf 50 tr td(ON)
0 0 10 20 30 40 50
0 0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE ()
RGS, GATE TO SOURCE RESISTANCE ()
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG -
BVDSS
VDS VDD
+
VDD
IAS 0.01
0 tAV
Figure 15. Unclamped Energy Test Circuit
(c)2004 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
FQD45N03L Rev. B1
FQD45N03L
Test Circuits and Waveforms (Continued)
VDS RL
VDD VDS
Qg(TOT)
VGS = 10V VGS Qg(5) VDD DUT Ig(REF) 0 VGS VGS = 1V Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
+
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON td(ON) RL VDS 90% tr
tOFF td(OFF) tf 90%
VGS
+
VDD DUT 0
10%
10%
90% VGS 50% PULSE WIDTH 50%
RGS
VGS
0
10%
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveform
(c)2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - T A ) P DM = ----------------------------Z JA
125 RJA = 33.32 + 23.84/(0.268+Area)
100
RJA (oC/W)
75
(EQ. 1)
50
In using surface mount devices such as the TO-252 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. R JA = 33.32 + ------------------------------------
25 0.01 0.1 1 10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting Pad Area
23.84 ( 0.268 + Area )
(EQ. 2)
(c)2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
PSPICE Electrical Model
.SUBCKT FQD45N03L 2 1 3 ; CA 12 8 8e-10 CB 15 14 9e-10 CIN 6 8 8.9e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 31.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
LGATE
rev October 2002
LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT VBAT + 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 21 16 EBREAK RLDRAIN DBREAK 11 + 17 18 5 DRAIN 2
RSLC2
5 51 ESG + GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 6 8 -
IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.41e-9 LSOURCE 3 7 3.99e-9
MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2e-3 RGATE 9 20 2.65 RLDRAIN 2 5 10 RLGATE 1 9 44.1 RLSOURCE 3 7 39.9 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*75),5))} .MODEL DBODYMOD D (IS = 1.28e-11 RS = 8.48e-3 TRS1 = 1.6e-3 TRS2 = 3e-6 XTI=2 CJO = 5.7e-10 TT = 9.5e-9 M = 0.57) .MODEL DBREAKMOD D (RS = 0.22 TRS1 = 8e-4 TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 3.7e-10 IS = 1e-30 N = 10 M = 0.48) .MODEL MMEDMOD NMOS (VTO = 1.99 KP = 8 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.65) .MODEL MSTROMOD NMOS (VTO = 2.4 KP = 32 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.62 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.5 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9e-4 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 2e-2 TC2 = 4e-5) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-7) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.6e-3 TC2 = -8e-6) .MODEL RVTEMPMOD RES (TC1 = -2.6e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -3.0 VOFF= -2.0) VON = -2.0 VOFF= -3.0) VON = -0.5 VOFF= 0.2) VON = 0.2 VOFF= -0.5)
(c)2004 Fairchild Semiconductor Corporation
+
DBODY
MWEAK MMED
FQD45N03L Rev. B1
FQD45N03L
SABER Electrical Model
REV October 2002 template FQD45N03L n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 1.28e-11, rs = 8.48e-3, trs1 = 1.6e-3, trs2 = 3e-6, xti=2, cjo = 5.7e-10, tt = 9.5e-9, m = 0.57) dp..model dbreakmod = (rs = 0.22, trs1 = 8e-4, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 3.7e-10, isl=10e-30, nl=10, m=0.48) m..model mmedmod = (type=_n, vto = 1.99, kp=8, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.4, kp = 32, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.62, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -3.0, voff = -2.0) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.0, voff = -3.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.2) LDRAIN sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.5) DPLCAP 5 c.ca n12 n8 = 8e-10 c.cb n15 n14 = 9e-10 c.cin n6 n8 = 8.9e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1
LGATE 10 RSLC1 51 RSLC2 ISCL ESG + GATE 1 RLGATE CIN EVTEMP RGATE + 18 22 9 20 6 6 8 50 RDRAIN EVTHRES 16 21 + 19 8 MMED MSTRO 8 DBREAK 11 MWEAK EBREAK + 17 18 RLDRAIN
DRAIN 2
DBODY
l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 4.41e-9 l.lsource n3 n7 = 3.99e-9
LSOURCE 7 RLSOURCE 18 RVTEMP
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9e-4, tc2 = 0 res.rdrain n50 n16 = 2e-3, tc1 = 2e-2, tc2 = 4e-5 res.rgate n9 n20 = 2.65 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 44.1 res.rlsource n3 n7 = 39.9 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 = 1e-7 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1e-2, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.6e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -1.6e-3, tc2 = -8e-6 spe.ebreak n11 n7 n17 n18 = 31.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B
SOURCE 3
RSOURCE RBREAK 17
15
CB + EDS 5 8
14
IT
19 VBAT +
8 RVTHRES
22
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/75))** 5)) } }
(c)2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
FQD45N03L
SPICE Thermal Model
REV October 2002 FQD45N03L_Thermal CTHERM1 th 6 1.3e-3 CTHERM2 6 5 1.5e-3 CTHERM3 5 4 1.6e-3 CTHERM4 4 3 1.7e-3 CTHERM5 3 2 5.8e-3 CTHERM6 2 tl 2e-2 RTHERM1 th 6 3.5e-3 RTHERM2 6 5 4.5e-3 RTHERM3 5 4 6.2e-2 RTHERM4 4 3 6.8e-1 RTHERM5 3 2 8.1e-1 RTHERM6 2 tl 8.3e-1
th
JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model FQD45N03L_Thermal template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.3e-3 ctherm.ctherm2 6 5 = 1.5e-3 ctherm.ctherm3 5 4 = 1.6e-3 ctherm.ctherm4 4 3 = 1.7e-3 ctherm.ctherm5 3 2 = 5.8e-3 ctherm.ctherm6 2 tl = 2e-2 rtherm.rtherm1 th 6 = 3.5e-3 rtherm.rtherm2 6 5 = 4.5e-3 rtherm.rtherm3 5 4 = 6.2e-2 rtherm.rtherm4 4 3 = 6.8e-1 rtherm.rtherm5 3 2 = 8.1e-1 rtherm.rtherm6 2 tl = 8.3e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2004 Fairchild Semiconductor Corporation
FQD45N03L Rev. B1
TRADEMARKS
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This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I9

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